Embodiments of the inventive concept relate generally to design verification tools. More particularly, embodiments of the inventive concept relate to computing systems capable of automatically generating one or more transactor(s) that may be used to verify the operating design of a bus.
Most contemporary electronic systems include at least one bus. The term “bus” typically denotes a set of conductive signal paths (e.g., wires, traces, through-vias, pads, terminal, and/or conductive regions, etc.) capable of respectively and/or collectively communicating one or more electrical signals. With increasing complexity of data, address and controls signals, bus architectures and usage approaches have become increasing sophisticated. In addition, many electronic systems are increasingly implemented as a system-on-chip (SoC).
Electronic systems including SoCs communicate a great variety of signals over one or more buses in response to the execution of certain functional block(s), each generically referred to as an “intellectual property” or IP. There are many different types and forms of IPs, and a great variety of IPs may be interoperated within an electronic system.
Thus, during execution an IP will provide one or more related signals to a bus. However, exercising respective IPs coupled to a particular bus during system testing can be very challenging. Since it so difficult to accurately control the provision of IP signals to a bus, a so-called “transactor” is commonly used. Conventionally, a transactor is manually generated by a system tester. However, this manual generation of transactor(s) replacing an IP takes a considerable amount of time. Further, as the number of IPs included in an SoC increases, the generation of corresponding transactors requires an ever more extended amount of time. Accordingly, the testing resources required to effectively verify the operation of a SoC bus have become increasingly burdensome.